Logic Component ![code/modules/wiremod/components/math/not.dm 6](git.png)
General logic unit with AND OR capabilities
Vars | |
input_port | The input port |
---|---|
result | The result from the output |
Var Details
input_port ![code/modules/wiremod/components/math/not.dm 12](git.png)
The input port
result ![code/modules/wiremod/components/math/not.dm 15](git.png)
The result from the output
General logic unit with AND OR capabilities
Vars | |
input_port | The input port |
---|---|
result | The result from the output |
The input port
The result from the output